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Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Applications
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Telecommunications: -- Inter- and intraoffice SONET/SDH -- Subscriber loop -- Metropolitan area networks High-speed data communications
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Description
The TA16 transponder performs the parallel-to-serialto-optical transport and optical transport-to-serial-toparallel function of the SONET/SDH protocol. The TA16 transmitter performs the bit serialization and optical transmission of SONET/SDH OC-48/STM-16 data that has been formatted into standard SONET/ SDH compliant, 16-bit parallel format. The TA16 receiver performs the optical-to-electrical conversion function and is then able to detect frame and byte boundaries and demultiplex the serial data into 16-bit parallel OC-48/STM-16 format. Note: The TA16 transponder does not perform bytelevel multiplexing or interleaving. Figure 1 shows a simplified block diagram of the TA16-type transponder. This device is a bidirectional module designed to provide a SONET or SDH compliant electro-optical interface between the SONET/ SDH photonic physical layer and the electrical section layer. The module contains a 2.5 Gbits/s optical transmitter and a 2.5 Gbits/s optical receiver in the same physical package along with the electronics necessary to multiplex and demultiplex sixteen 155 Mbits/s electrical channels. Clock synthesis and clock recovery circuits are also included within the module. In the transmit direction, the transponder module multiplexes sixteen 155 Mbits/s LVPECL electrical data signals into an optical signal at 2488.32 Mbits/s for launching into optical fiber. An internal 2.488 GHz reference oscillator is phase-locked to an external 155 MHz data timing reference.
The TA16-Type transponders integrate up to 15 discrete ICs and optical components, including a 2.5 Gbits/s optical transmitter and receiver pair, all in a single, compact package.
Features
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2.5 Gbits/s optical transmitter and receiver with 16-channel 155 Mbits/s multiplexer/demultiplexer Available with 1.31 m Fabry-Perot laser transmitter and PIN receiver for intraoffice applications, and 1.31 m or 1.55 m DFB laser transmitters and PIN or APD receiver for short-haul to long-haul applications Pigtailed low-profile package Differential LVPECL data interface Operating case temperature range: 0 C to 65 C Automatic transmitter optical power control Laser bias monitor output Optical transmitter disable input SONET frame-detect enable Loss of signal, loss of sync, loss of framing alarms Diagnostic loopback capability Line loopback operation
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Table of Contents
Contents Page Tables Page
Features .................................................................... 1 Applications ............................................................... 1 Description ................................................................ 1 Absolute Maximum Ratings ....................................... 3 Pin Information .......................................................... 5 Pin Descriptions ........................................................ 6 Functional Description ............................................ 12 Receiver ............................................................. 12 Transmitter ......................................................... 12 Loopback Modes ................................................ 13 Transponder Interfacing ...................................... 13 Optical Characteristics ............................................ 14 Electrical Characteristics ......................................... 15 Timing Characteristics ............................................ 17 Transmitter Data Input Timing ............................ 17 Input Timing Mode 1 .......................................... 18 Input Timing Mode 2 .......................................... 19 Forward Clocking ............................................... 20 PCLK-to-PICLK Timing ......................................... 21 PHERR/PHINIT ................................................... 22 Receiver Framing ............................................... 24 Qualification and Reliability ..................................... 26 Laser Safety Information ........................................ 26 Class 1 Laser Product......................................... 26 Electromagnetic Emissions and Immunity .......... 26 Outline Diagram ...................................................... 27 Ordering Information ............................................... 28 Related Product Information .................................... 28
Table 1. TA16-Type Transponder Pinout .................. 6 Table 2. TA16-Type Transponder Input Pin Descriptions ......................................... 10 Table 3. TA16-Type Transponder Output Pin Descriptions ......................................... 11 Table 4. OC48/STM-16 Transmitter Optical Characteristics ........................................... 14 Table 5. OC48/STM-16 Receiver Optical Characteristics ........................................... 14 Table 6. Transmitter Electrical I/O Characteristics .. 15 Table 7. Receiver Electrical I/O Characteristics ...... 16 Table 8. Power Supply Characteristics ................... 16 Table 9. Transmitter ac Timing Characteristics ....... 23 Table 10. Receiver ac Timing Characteristics ......... 23 Table 11. Ordering Information ................................ 28 Table 12. Related Product Information .................... 28
Figures
Page
Figure 1. TA16-Type Transponder Block Diagram .... 4 Figure 2. TA16-Type Transponder Pinout ................. 5 Figure 3. Transponder Interfacing............................ 13 Figure 4. Block Diagram Timing Mode 1.................. 18 Figure 5. Block Diagram Timing Mode 2.................. 19 Figure 6. Forward Clocking of TA16 Transmitter.....20 Figure 7. PCLK-to-PICLK Timing...............................21 Figure 8. PHERR/PHINIT Timing.............................22 Figure 9. ac Input Timing .........................................22 Figure 10. Receiver Output Timing Diagram ...........23 Figure 11. Frame and Byte Detection ......................24 Figure 12. OOF Timing (FRAMEN = High) ..............24 Figure 13. FRAMEN Timing .....................................25 Figure 14. Interfacing to TxREFCLK Input................. 25
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
In the receive direction, the transponder module receives a 2488.32 Mbits/s optical signal and converts it to an electrical signal, extracts a clock signal, and then demultiplexes the data into sixteen 155 Mbits/s differential LVPECL data signals. The optical receiver is available with either a PIN photodetector or with an APD photodetector. The receiver operates over the wavelength range of 1.1 m to 1.6 m and is fully compliant to SONET/SDH OC-48/STM-16 physical layer specifications as shown in Table 5, Optical Characteristics.
Description (continued)
The optical transmitter is available with either a 1.31 m Fabry-Perot laser for short-reach applications or 1.31 m and 1.55 m DFB lasers for intermediate- to long-reach applications. The optical output signal is SONET and ITU compliant for OC-48/STM-16 applications as shown in Table 4, Optical Characteristics.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect reliability. Parameter Operating Case Temperature Range Storage Case Temperature Range Supply Voltage Voltage on Any LVPECL Pin High-speed LVPECL Output Source Current Static Discharge Voltage1 Relative Humidity (noncondensing) Receiver Optical Input Power--Biased: APD PIN Minimum Fiber Bend Radius
1. Human body model.
Symbol TC TS -- -- -- ESD RH PIN PIN --
Min 0 -40 -0.5 0 -- -- -- -- -- 1.25 (31.8)
Max 75 85 5.5 VCC 50 500 85 0 8 --
Unit C C V -- mA V % dBm dBm in. (mm)
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Block Diagram
TXDIS LSRBIAS LSR ALRM LPM TXD[0:15]N PICLKP/N PHINIT PHERR PCLKP/N TXREFCLKP/N LOCKDET LLOOP RESET DLOOP OOF FRAMEN SEARCH FP POCLKP/N 2 FRAME/BYTE DETECT TIMING GEN 2 2 CLOCK DIVIDER AND PHASE DETECT 16 2 TIMING GENERATION MUX 16:1 PARALLEL TO SERIAL MUX TXD[0:15]P 16
D OC-48/STM-16 OPTICAL TRANSMITTER
MUX
CK RXQ[0:15]P RXQ[0:15]N LOS IPDMON 16 16 MUX 1:16 SERIAL TO PARALLEL D
OC-48/STM-16 OPTICAL RECEIVER W/CLOCK RECOVERY
1-1011(F).e
Figure 1. TA16-Type Transponder Block Diagram
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Information
80
70
60
50
40
30
20
10
1
FGND NC NC NC NC RXDGND RXQ00N RXQ00P RXQ02N RXQ02P RXDGND RXQ04N RXQ04P RXQ06N RXQ06P RXDGND RXQ08N RXQ08P RXQ10N RXQ10P RXDGND RXQ12N RXQ12P RXQ14N RXQ14P RXDGND NC NC NC RXDGND RXAGND RXAGND RX3.3A RXAGND RXAGND NC RX3.3D RX3.3D RXDGND FRAMEN FP NC DLOOP NC LSRBIAS LSRALM LPM TXAGND TX3.3A TX3.3A TXAGND TX3.3D TX3.3D TXDGND LOCKDET PICLKN PICLKP TXDGND TXD01N TXD01P TXD03N TXD03P TXDGND TXD05N TXD05P TXD07N TXD07P TXDGND TXD09N TXD09P TXD11N TXD11P TXDGND TXD13N TXD13P TXD15N TXD15P TXDGND IPDMON FGND
FGND NC NC NC NC RXDGND RXQ01N RXQ01P RXQ03N RXQ03P RXDGND RXQ05N RXQ05P RXQ07N RXQ07P RXDGND RXQ09N RXQ09P RXQ11N RXQ11P RXDGND RXQ13N RXQ13P RXQ15N RXQ15P RXDGND NC NC NC NC POCLKN POCLKP RX3.3A RXAGND RXAGND SEARCH RX3.3D RX3.3D RXDGND OOF RXDGND LOS LLOOP PHERR NC TXDIS PHINIT NC TX3.3A TX3.3D TXAGND TXDGND PCLKN PCLKP TXDGND TXD00N TXD00P TXDGND TXD02N TXD02P TXD04N TXD04P TXDGND TXD06N TXD06P TXD08N TXD08P TXDGND TXD10N TXD10P TXD12N TXD12P TXDGND TXD14N TXD14P TXREFCLKN TXREFCLKP TXDGND RESET FGND
160
150
RX
140
130
120
110
100
TX
90
TOP VIEW
81
1-1014(F).r2
Figure 2. TA16-Type Transponder Pinout
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Pin Descriptions
Table 1. TA16-Type Transponder Pinout Pin # 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 6 Pin Name FGND IPDMON TxDGND TxD15P TxD15N TxD13P TxD13N TxDGND TxD11P TxD11N TxD09P TxD09N TxDGND TxD07P TxD07N TxD05P TxD05N TxDGND TxD03P TxD03N TxD01P TxD01N TxDGND PICLKP PICLKN LOCKDET TxDGND Tx3.3D Tx3.3D TxAGND Tx3.3A Tx3.3A TxAGND LPM LSRALRM LSRBIAS NC DLOOP NC FP FRAMEN RxDGND I/O I O I I I I I I I I I I I I I I I I I I I I I I I O I I I I I I I O O O -- I -- O I I Logic Supply Analog Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVTTL Supply Supply Supply Supply Supply Supply Supply Analog Analog Analog -- LVTTL -- LVPECL LVTTL Supply Ground1 Description Frame Receiver Photodiode Current Monitor Transmitter Digital Ground Transmitter 155 Mbits/s MSB Data Input Transmitter 155 Mbits/s MSB Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Byte-Aligned Parallel Input Clock at 155 MHz Byte-Aligned Parallel Input Clock ar 155 MHz Lock Detect Transmitter Digital Ground Transmitter 3.3 V Digital Supply Transmitter 3.3 V Digital Supply Transmitter Analog Ground Transmitter 3.3 V Analog Supply Transmitter 3.3 V Analog Supply Transmitter Analog Ground Laser Power Monitor Laser Degrade Alarm Transmitter Laser Bias Output No User Connection Permitted Diagnostic Loopback No User Connection Permitted Frame Pulse Frame Enable Receiver Digital Ground
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions (continued)
Table 1. TA16-Type Transponder Pinout (continued) Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Pin Name Rx3.3D Rx3.3D NC RxAGND RxAGND Rx3.3A RxAGND RxAGND RxDGND NC NC NC RxDGND RxQ14P RxQ14N RxQ12P RxQ12N RxDGND RxQ10P RxQ10N RxQ08P RxQ08N RxDGND RxQ06P RxQ06N RxQ04P RxQ04N RxDGND RxQ02P RxQ02N RxQ00P RxQ00N RxDGND NC NC NC NC FGND FGND RESET TxDGND TxREFCLKP TxREFCLKN I/O I I -- I I I I I I -- -- -- I O O O O I O O O O I O O O O I O O O O I -- -- -- -- I I I I I I Logic Supply Supply -- Supply Supply Supply Supply Supply Supply -- -- -- Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply -- -- -- -- Supply Supply LVTTL Supply LVPECL LVPECL Description Receiver 3.3 V Digital Supply Receiver 3.3 V Digital Supply No User Connection Permitted Receiver Analog Ground Receiver Analog Ground Receiver 3.3 V Analog Supply Receiver Analog Ground Receiver Analog Ground Receiver Digital Ground No User Connection Permitted No User Connection Permitted No User Connection Permitted Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s LSB Data Output Receiver 155 Mbits/s LSB Data Output Receiver Digital Ground No User Connection Permitted No User Connection Permitted No User Connection Permitted No User Connection Permitted Frame Ground1 Frame Ground1 Master Reset Transmitter Digital Ground Transmitter 155 Mbits/s Reference Clock Input Transmitter 155 Mbits/s Reference Clock Input 7
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
Agere Systems Inc.
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Pin Descriptions (continued)
Table 1. TA16-Type Transponder Pinout (continued) Pin # 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 8 Pin Name TxD14P TxD14N TxDGND TxD12P TxD12N TxD10P TxD10N TxDGND TxD08P TxD08N TxD06P TxD06N TxDGND TxD04P TxD04N TxD02P TxD02N TxDGND TxD00P TxD00N TxDGND PCLKP PCLKN TxDGND TxAGND Tx3.3D Tx3.3A NC PHINIT TXDIS NC PHERR LLOOP LOS RxDGND OOF RxDGND Rx3.3D Rx3.3D SEARCH RxAGND RxAGND Rx3.3A I/O I I I I I I I I I I I I I I I I I I I I I O O I I I I -- I I -- O I O I I I I I O I I I Logic LVPECL LVPECL SUPPLY LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL Supply LVPECL LVPECL Supply Supply Supply Supply -- LVPECL TTL -- LVPECL LVTTL LVTTL Supply LVTTL Supply Supply Supply LVTTL Supply Supply Supply Description Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter 155 Mbits/s Data Input Transmitter Digital Ground Transmitter 155 Mbits/s LSB Data Input Transmitter 155 Mbits/s LSB Data Input Transmitter Digital Ground Transmitter Parallel Reference Clock Output Transmitter Parallel Reference Clock Output Transmitter Digital Ground Transmitter Analog Ground Transmitter Digital 3.3 V Supply Transmitter Analog 3.3 V Supply No User Connection Permitted Phase Initialization Transmitter Disable No User Connection Permitted Phase Error Line Loopback (active-low) Loss of Signal Receiver Digital Ground Out of Frame (enable frame detection) Receiver Digital Ground Receiver Digital 3.3 V Supply Receiver Digital 3.3 V Supply Frame Search Output Receiver Analog Ground Receiver Analog Ground Receiver Analog 3.3 V Supply Agere Systems Inc.
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions (continued)
Table 1. TA16-Type Transponder Pinout (continued) Pin # 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name POCLKP POCLKN NC NC NC NC RxDGND RxQ15P RxQ15N RxQ13P RxQ13N RxDGND RxQ11P RxQ11N RxQ09P RxQ09N RxDGND RxQ07P RxQ07N RxQ05P RxQ05N RxDGND RxQ03P RxQ03N RxQ01P RxQ01N RxDGND NC NC NC NC FGND I/O O O -- -- -- -- I O O O O I O O O O I O O O O I O O O O I -- -- -- -- I Logic LVPECL LVPECL -- -- -- -- Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply LVPECL LVPECL LVPECL LVPECL Supply -- -- -- -- Supply Description Byte-Aligned Parallel Output Clock at 155 MHz Byte-Aligned Parallel Output Clock at 155 MHz No User Connection Permitted No User Connection Permitted No User Connection Permitted No User Connection Permitted Receiver Digital Ground Receiver MSB 155 Mbits/s Data Output Receiver MSB 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver 155 Mbits/s Data Output Receiver Digital Ground No User Connection Permitted No User Connection Permitted No User Connection Permitted No User Connection Permitted Frame Ground1
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Pin Descriptions (continued)
Table 2. TA16-Type Transponder Input Pin Descriptions Pin Name TxD[0:15]P TxD[0:15]N Pin Description
16-bit Differential LVPECL Parallel Input Data Bus. TxD15P/N is the most significant bit of the input word and is the first bit serialized. TxD00P/N is the least significant bit of the input word and is the last bit serialized. TxD[0:15]P/N is sampled on the rising edge of PICLK. PICLKP Differential LVPECL Parallel Input Clock. A 155 MHz nominally 50% duty cycle PICLKN input clock to which TxD[0:15]P/N is aligned. The rising edge of PICLK transfers the data on the 16 TxD inputs into the holding register of the parallel-to-serial converter. TxREFCLKP Differential LVPECL Low Jitter 155.520 MHz Input Reference Clock. This input is TxREFCLKN used as the reference for the internal clock frequency synthesizer which generates the 2.5 GHz bit rate clock used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which transfers the 16-bit parallel input data from the input holding register into the parallel-to-serial shift register. Input is internally terminated and biased. See discussion on interfacing, page 13. TxDIS Transmitter Disable Input. A logic HIGH on this input pin shuts off the transmitter's laser so that there is no optical output. DLOOP Diagnostic Loopback Enable (LVTTL). When the DLOOP input is low, the 2.5 Gbits/s serial data stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel converter along with an internally generated bit synchronous serial clock. The received serial data path from the optical receiver is disabled. LLOOP Line Loopback Enable (LVTTL). When LLOOP is low, the 2.5 Gbits/s serial data and recovered clock from the optical receiver are looped directly back to the optical transmitter. The multiplexed serial data from the parallel-to-serial converter is ignored. PHINIT Phase Initialization (LVPECL). A rising edge on this input will realign the internal timing associated with clocking data into and out of the internal FIFO. For a detailed explanation, see the section on Transmitter Data Input Timing on page 17. FRAMEN Frame Enable Input (LVTTL). Enables the frame detection circuitry to detect A1 A2 byte alignment and to lock to a word boundary. The TA16 transponder will continually perform frame acquisition as long as FRAMEN is held high. When this input is low, the frame-detection circuitry is disabled. Frame-detection process is initiated by rising edge of out-of-frame pulse. OOF Out of Frame (LVTTL). This input indicator is typically generated by external SONET/SDH overhead monitor circuitry in response to a state in which the frame boundaries of the received SONET/SDH signal are unknown, i.e., after system reset or loss of synchronization. The rising edge of the OOF input initiates the frame detection function if FRAMEN is high. The FP output goes high when the frame boundary is detected in the incoming serial data stream from the optical receiver. RESET Master Reset (LVTTL). Reset input for the multiplexer/demultiplexer. A low on this input clears all buffers and registers. During reset, POCLK and PCLK do not toggle.
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions (continued)
Table 3. TA16-Type Transponder Output Pin Descriptions Pin Name Pin Description
RxQ[0:15]P 16-bit Differential LVPECL Parallel Output Data Bus. RxQ[0:15] is the RxQ[0:15]N 155 Mbyte/s 16-bit output word. RxQ15P/N is the most significant bit of the received word and is the first bit serialized. RxQ00P/N is the least significant bit of the received word and is the last bit serialized. RxQ[0:15]P/N is updated on the falling edge of POCLk. POCLKP Differential LVPECL Parallel Output Clock. A 155 MHz nominally 50% duty cycle, POCLKN byte rate output clock that is aligned to the RxQ[0:15] byte serial output data. RxQ[0:15] and FP are updated on the falling edge of POCLK. FP Frame Pulse (LVPECL). Indicates frame boundaries in the received serial data stream. If framing pattern detection is enabled (FRAMEN high and OOF), FP pulses high for one POCLK cycle when a 32-bit sequence matching the framing pattern is detected in the received serial data. FP is updated on the falling edge of POCLK. SEARCH A1 A2 Frame Search Output (LVTTL). A high on this output pin indicates that the frame detection circuit is active and is searching for a new A1 A2 byte alignment. This output will be high during the entire A1 A2 frame search. Once a new alignment is found, this signal will remain high for a minimum of one 155 MHz clock period beyond the third A2 byte before it will be set low. LOS Loss of Signal (LVTTL). A low on this output indicates a loss of lock by the clock recovery circuit in the optical receiver. LSRBIAS Laser Bias (Analog). Provides an indication of the health of the laser in the transmitter. This output changes at the rate of 20 mV/mA of bias current. If this output voltage reaches 1.4 V (70 mA of bias), the automatic power control circuit is struggling to maintain output power. This may indicate that the transmitter has reached an end-of-life condition. LSRALRM Laser Degrade Alarm (5 V CMOS). A logic low on this output indicates that the transmitter's automatic power control circuits are unable to maintain the nominal output power. This output becomes active when the optical output power degrades 2 dB below the nominal operating power. LPM Laser Power Monitor (Analog). Provides an indication of the output power level from the transmitter laser. This output is set at 500 mV for the nominal transmitter optical output power. If the optical power decreases by 3 dB, this output will drop to approximately 250 mV, and if the output power should increase by 3 dB, this output will increase to 1000 mV. PCLKP/N Parallel Byte Clock (Differential LVPECL). A byte-rate reference clock generated by dividing the internal 2.488 GHz serial bit clock by 16. This output is normally used to synchronize byte-wide transfers from upstream logic into the TA16 transponder. See timing discussion for additional details, page 17. PHERR Phase Error Signal (Single-Ended LVPECL). This signal pulses high during each PCLK cycle for which there is potential setup/hold timing violations between the internal byte clock and the PICLK timing domains. PHERR is updated on the falling edge of the PICLK output. For a detailed explanation, see the section on Transmitter Data Input Timing on page 17. IDPMON Receiver Photodiode Current Monitor (Analog). This output provides a current output that is a mirror of the photocurrent generated by the optical receiver's photodiode (APD or PIN). LOCKDET Lock Detect (LVTTL). This output goes low after the transmit side PLL has locked to the clock signal provided at the TXREFCLK input pins. LOCKDET is an asynchronous output. Agere Systems Inc. 11
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Functional Description
Receiver
The optical receiver in the TA16-type transponder is optimized for the particular SDH/SONET application segment in which it was designed to operate and will have either an APD or PIN photodetector. The detected serial data output of the optical receiver is connected to a clock and data recovery circuit (CDR), which extracts a 2488.32 MHz clock signal. This recovered serial bit clock signal and a retimed serial data signal are presented to the 16-bit serial-to-parallel converter and to the frame and byte detection logic. The serial-to-parallel converter consists of three 16-bit registers. The first is a serial-in parallel-out shift register, which performs serial-to-parallel conversion. The second is an internal 16-bit holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte detection logic. On the falling edge of the free-running POCLK signal, the data in the holding register is transferred to the output holding register where it becomes available as RxQ[0:15]. The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by an A2 byte. Framing pattern detection is enabled and disabled by the FRAMEN input. The frame detection process is started by a rising edge on OOF while FRAMEN is active (FRAMEN= high). It is disabled when a framing pattern is detected. When framing pattern detection is enabled (FRAMEN = high), the framing pattern is used to locate byte and frame boundaries in the incoming serial data stream from the CDR circuits. During this time, the parallel output data bus (RxQ[0:15]) will not contain valid data. The timing generator circuitry takes the located byte boundary and uses it to block the incoming serial data stream into bytes for output on the parallel output data bus (RxQ[0:15]). The frame boundary is reported on the framing pulse (FP) output when any 32-bit pattern matching the framing pattern is detected in the incoming serial data stream. When framing detection is disabled (FRAMEN = low), the byte boundary is fixed at the location found when frame detection was previously enabled.
element and can operate at either 1310 nm or 1550 nm. The transmitter is driven by a serial data stream developed in the parallel-to-serial conversion logic and by a 2488.32 MHz serial bit clock signal synthesized from the 155.52 MHz TxREFCLK input. The parallel-to-serial converter block shown in Figure 1 is comprised of two byte-wide registers. The first register latches the 16 bits of parallel input data (TxD[0:15]) on the rising edge of PICLK. The second register is a 16-bit parallel-load serial-out shift register that is loaded from the input register. An internally generated byte clock, which is phase aligned to the 2488.32 MHz serial transmit clock, activates the data transfer between the input register and the parallel-to-serial register. The clock divider and phase detect circuitry shown in Figure 1 generates internal reference clocks and timing functions for the transmitter. Therefore, it is important that the TxREFCLK input is generated from a precise and stable source. To prevent internal timing signals from producing jitter in the transmitted serial data that exceeds the SDH/SONET jitter generation requirements of 0.01 UI, it is required that the TxREFCLK input be generated from a crystal oscillator or other source having a frequency accuracy better than 20 ppm. In order to meet the SDH/SONET requirement, the reference clock jitter must be guaranteed to be less than 1 ps rms over the 12 kHz to 20 MHz bandwidth. When used in SONET network applications, this input clock must be derived from a source that is synchronized to the primary reference clock (stratum 1 clock). The timing generation circuitry provides two separate functions. It develops a byte rate clock that is synchronized to the 2488.32 MHz transmit serial clock, and it provides a mechanism for aligning the phase between the incoming byte clock (PICLK) and the clock which loads the parallel data from the input register into the parallel-to-serial shift register. The PCLK output is a byte rate (155 MHz) version of the serial transmit clock and is intended for use by upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the parallel data coming into the transmitter and the subsequent parallel-to-serial timing functions. The timing generator also provides a feedback reference clock to the phase detector for use by the transmit serial clock synthesizer (for additional discussions, see transmitter input options, page 17.)
Transmitter
The optical transmitter in the TA16-type transponder is optimized for the particular SDH/SONET segment in which it is designed to operate. The transmitter will have either a Fabry-Perot or a DFB laser as the optical 12 12
Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Transponder Interfacing
The TxD[0:15]P/N and PICLKP/N inputs and the RxQ[0:15]P/N, POCLKP/N, and PCLKP/N outputs are high-speed (155 Mbits/s), LVPECL differential data and clock signals. To maintain optimum signal fidelity, these inputs and outputs must be connected to their terminating devices via 50 controlled-impedance transmission lines. The transmitter inputs (TxD[0:15]P/N, TxREFCLKP/N, and PICLKP/N) must be terminated as close as possible to the TA16 transponder connector with a Thevenin equivalent impedance equal to 50 3/4 terminated to Vcc - 2V. The receiver outputs (RxQ[0:15]P/N, POCLKP/N, and PCLKP/N) must be terminated as close as possible to the device (IC) that these signals interface to with a Thevenin equivalent impedance equal to 50 terminated to Vcc - 2 V. Figure 3, below, shows one example of the proper terminations. Other methods may be used, provided they meet the requirements stated above. TxREFCLKP/N. The reference clock input is different than the TxD and PICLK inputs because it is internally terminated, ac-coupled, and self-biased. Therefore, it must be treated somewhat differently than the TxD and PICLK inputs. Figure 14 shows the proper method for connecting the TxREFCLK input.
3.3 V
Functional Description (continued)
Loopback Modes
The TA16 transponder is capable of operating in either of two loopback modes: diagnostic loopback or line loopback. Line Loopback When LLOOP is pulled low, the received serial data stream and recovered 2488.32 MHz serial clock from the optical receiver are connected directly to the serial data and clock inputs of the optical transmitter. This establishes a receive-to-transmit loopback at the serial line rate. Diagnostic Loopback When DLOOP is pulled low, a loopback path is established from the transmitter to the receiver. In this mode, the serial data from the parallel-to-serial converter and the transmit serial clock are looped back to the serialto-parallel converter and the frame and byte detect circuitry, respectively.
SONET/SDH INTERFACE IC 130 50 IMPEDANCE TRANSMISSION LINES 80 80 CONNECTOR 130
TA16-TYPE TRANSPONDER TxD[0:15]P (LVPECL) MUX TxD[0:15]N (LVPECL) Tx
TxLINE
3.3 V
130
130 50 IMPEDANCE TRANSMISSION LINES
RxD[0:15]P (LVPECL) DEMUX RxD[0:15]N (LVPECL) Rx
RxLINE
80
80
1-1054(F)
Figure 3. Transponder Interfacing
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Optical Characteristics
Minimum and maximum values specified over operating case temperature range at 50% duty cycle data signal. Typical values are measured at room temperature unless otherwise noted. Table 4. OC48/STM-16 Transmitter Optical Characteristics (Tc = 0 C to 65 C) Parameter Average Output Power: Intraoffice (F-P laser) Short Haul (DFB laser) Long Haul: 1.3 m DFB Laser 1.55 m DFB Laser Operating Wavelength: Intraoffice (F-P laser) Short Haul (DFB laser) Long Haul (1.3 m DFB laser) Long Haul (1.55 m DFB laser) Spectral Width: Intraoffice (F-P laser) Short Haul and Long Haul (DFB laser) 2 Side-mode Suppression Ratio (DFB laser) 3 Extinction Ratio4 Optical Rise and Fall Times Eye Mask of Optical Output 5, 6 Jitter Generation
1
Symbol Po Po Po Po rms 20 SSR re tR, tF
Min -10 -5 -2 -2 1270 1270 1280 1500 -- -- 30 8.2 --
Typ -5 -2 0 0 -- -- -- -- -- -- -- -- --
Max -3 0 2 3 1360 1360 1335 1580 4 1 -- -- 200
Unit dBm dBm dBm dBm nm nm nm nm nm nm dB dB ps
Compliant with GR-253 and ITU-T G.957 Compliant with GR-253 and ITU-T G.958
1. Output power definitions and measurements per ITU-T Recommendation G.957. 2. Full spectral width measured 20 dB down from the central wavelength peak under fully modulated conditions. 3. Ratio of the average output power in the dominant longitudinal mode to the power in the most significant side mode under full modulated y conditions. 4. Ratio of logic 1 output power to logic 0 output power under fully modulated conditions. 5. GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria. 6. ITU-T Recommendation G.957, Optical Interfaces for Equipment and Systems Relating to the Synchronous Digital Hierarchy.
Table 5. OC48/STM-16 Receiver Optical Characteristics (Tc = 0 C to 65 C)
Parameter Average Receiver Sensitivity : PIN Receiver (intraoffice, short haul) APD Receiver (long haul) Maximum Optical Power: PIN Receiver APD Receiver (long reach) Link Status Switching Threshold Decreasing Light Input: APD PIN Link Status Response Time Optical Path Penalty (1310 nm/1550 nm) Receiver Reflectance Jitter Tolerance and JitterTransfer
1. At 1310 nm, 1 x 10
-10 23
Symbol
Min -20 -29 1 -6
Typ -25 -34 -- --
Max -- --
-- --
Unit dBm dBm dBm dBm
1
PRMIN PRMIN
PRMAX
RMAX
LSTD LSTD -- -- --
-- -- 3 -- --
TBD TBD -- -- --
-- -- 100 1/2 -27
dBm dBm s dB dB
Compliant with GR-253 and ITU-T G.958
BER, 2
- 1 pseudorandom data input.
14
Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Electrical Characteristics
Table 6. Transmitter Electrical I/O Characteristics (TC = 0 C to 65 C, VCC = 3.3 V 5%) Parameter Parallel Input Clock Parallel Clock in Duty Cycle Reference Clock Frequency Tolerance Reference Clock Jitter (in 12 KHz to 20 MHz band) Reference Clock Input Duty Cycle Reference Clock Rise and Fall Times1 Reference Clock Signal Levels:2 Diff. Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Input Data Signal Levels: Input High, VIH Input Low, VIL Input Voltage Swing, VIN Transmitter Disable Input3 Transmitter Enable Input3 Laser Bias Voltage Output4 Laser Power Monitor Output5 Laser Degrade Alarm: Output High, VOH Output Low, VOL Phase Initialization: Input High, VIH Input Low, VIL Phase Error6: Output High, VOH Output Low, VOL Line Loopback Enable: Active-Low: Input High, VIH Input Low, VIL
1. 2. 3. 4. 5. 6.
Symbol PICLKP/N -- TxREFCLKP/N -- -- --
Logic Diff. LVPECL -- Diff. LVPECL -- -- -- Diff. LVPECL
Min 153.90 40 -20 -- 45 --
Typ 155.52 -- -- -- -- --
Max 157.00 60 20 1 55 1.5
Unit MHz % ppm ps rms % ns
VINDIFF VINSINGLE RDIFF TxD[0:15]P/N
300 150 80 VCC - 1.2 VCC - 2.0 300 2.0 0 0 35 4.5 0 VCC - 1.0 VCC - 2.3 VCC - 1.2 VCC - 2.2
-- -- 100 -- -- -- -- -- 200 500 -- -- -- -- -- --
1200 600 120 VCC - 0.3 VCC - 1.5 -- 5.5 0.8 1600 1000 5.2 0.4 VCC - 0.57 VCC - 1.44 VCC - 0.65 VCC - 1.5
mV mV V V mV V V mV mV V V V V V V
Diff. LVPECL
TxDIS TxEN LSRBIAS LPM LSRALM
TTL (5 V) TTL (5 V) Analog Analog 5V CMOS SingleEnded LVPECL SingleEnded LVPECL LVTTL
PHINIT
PHERR
LLOOP
2.0 0
-- --
VCC + 1.0 0.8
V V
20% to 80%. Internally biased and ac-coupled. See Figure 13. The transmitter is normally enabled and only requires an external voltage to disable. Output conversion factor is 20 mV/mA of laser bias current. Set at 500 mV at nominal output power; will track PO linearly (-3 dB = 250 mV, +3 dB = 1000 mV). Terminated into 220 to GND with 100 line-to-line.
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Electrical Characteristics (continued)
Table 6. Transmitter Electrical I/O Characteristics (TC = 0 C to 65 C, VCC = 3.3 V 5%) (continued) Diagnostic Loopback Enable: Active-Low: Input High, VIH Input Low, VIL Parallel Output Clock:6 Output High, VOH Output Low, VOL S-E Output Voltage Swing, VSINGLE Diff. Voltage Swing, VDIFF
1. 2. 3. 4. 5. 6.
DLOOP
LVTTL 2.0 0 -- -- -- -- -- -- VCC + 1.0 0.8 VCC - 0.6 VCC - 1.45 950 1900 V V V V mV mV
PCLKP/N
Diff. LVPECL
VCC - 1.15 VCC - 1.95 400 800
20% to 80%. Internally biased and ac-coupled. See Figure 13. The transmitter is normally enabled and only requires an external voltage to disable. Output conversion factor is 20 mV/mA of laser bias current. Set at 500 mV at nominal output power; will track PO linearly (-3 dB = 250 mV, +3 dB = 1000 mV). Terminated into 220 to GND with 100 line-to-line.
Table 7. Receiver Electrical I/O Characteristics (Tc = 0 C to 65 C, Vcc = 3.3 V 5%) Parameter Parallel Output Clock: Output High, VOH Output Low, VOL POCLk Duty Cycle Output Data Signal Levels : Output High, VOH Output Low, VOL RxQ[0:15] Rise/Fall Time2 Frame Pulse: Output High, VOH Output Low, VOL Loss-of-Signal Output: Output High, VOH Output Low, VOL Out-of-Frame Input: Input High, VIH Input Low, VIL Frame Enable Input
1
Symbol POCLKP/N
Logic Diff. LVPECL
Min VCC - 1.3 VCC - 2.00 40 2.275 1.490 -- VCC - 1.3 VCC - 2.00
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max VCC - 0.7 VCC - 1.4 60 2.420 1.680 1.0 VCC - 0.7 VCC - 1.4 VCC 0.4 VCC + 1.0 0.8 VCC + 1.0 0.8
Unit V V % V V ns V V V V V V V V
-- RxQ[0:15]P/N
-- Diff. LVPECL -- LVPECL
-- FP
LOS
LVTTL 2.4 0
OOF
LVTTL 2.00 0.0
FRAMEN
LVTTL 2.00 0.0
1. Terminated into 330 to ground. 2. 20% to 80%, 330 to ground.
Table 8. Power Supply Characteristics (Tc = 0 C to 65 C) Parameter Supply Voltage dc Power Supply Current Drain1 Power Dissipation Symbol VCC ICC PDISS Min 3.13 -- -- Typ 3.3 1800 6 Max 3.47 2300 -- Unit V mA W
1. Does not include output termination resistor current drain.
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
During normal operation, the incoming data is passed from the PICLK input timing domain to the internally generated divide-by-16 PCLK timing domain. Although the frequency of PICLK and PCLK are the same, their phase relationship is arbitrary. To prevent errors caused by short setup or hold times between the two domains, the timing generator circuitry monitors the phase relationship between PICLK and PCLK. When an FIFO timing violation is detected, the phase error (PHERR) signal pulses high. If the condition persists, PHERR will remain high. When PHERR is fed back into the PHINIT input (by shorting them on the printed-circuit board [PCB]), PHINIT will initialize the FIFO if PHINIT is held high for at least two byte clocks. The initialization of the FIFO prevents PCLK and PICLK from concurrently trying to read and write over the same FIFO bank. During realignment, one to three bytes (16-bits wide) will be lost. Alternatively, the customer logic can take in the PHERR signal, process it, and send an output to the PHINIT input in such a way that only idle bytes are lost during the initialization of the FIFO. Once the FIFO has been initialized, PHERR will go inactive.
Timing Characteristics
Transmitter Data Input Timing
The TA16 transponder utilizes a unique FIFO to decouple the internal and external (PICLK) clocks. The FIFO can be initialized, which allows the system designer to have an infinite PCLK-to-PICLK delay through this interfacing logic (ASIC or commercial chip set). The configuration of the FIFO is dependent upon the I/O pins, which comprise the synch timing loop. This loop is formed from PHERR to PHINIT and PCLK to PICLK. The FIFO can be thought of as a memory stack that can be initialized by PHINT or LOCKDET. The PHERR signal is a pointer that goes high when a potential timing mismatch is detected between PICLK and the internally generated PCLK clock. When PHERR is fed back to PHINIT, it initializes the FIFO so that it does not overflow or underflow. The internally generated divide-by-16 clock is used to clock out data from the FIFO. PHINIT and LOCKDET signals will center the FIFO after the third PICLK pulse. This is done to ensure that PICLK is stable. This scheme allows the user to have an infinite PCLK to PICLK delay through the ASIC. Once the FIFO is centered, the PCLK and PICLK can have a maximum drift of 5 ns.
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Timing Characteristics (continued)
Input Timing Mode 1
In the configuration shown in Figure 4, PHERR to PHINIT has a zero delay (shorted on the PCB) and the PCLK is used to clock 16-bit-wide data out of the customer ASIC. The FIFO in the multiplexer is 16-bits wide and six registers deep. The PCLK and PICLK signals respectively control the READ and WRITE counters for the FIFO. The data bank from the FIFO has to be read by the internally
generated clock (PCLK) only once after it has been written by the PICLK input. Since the delay in the customer ASIC is unknown, the two clocks (PCLK and PICLK) might drift in respect to each other and try to perform the read and writer operation on the same bank in the FIFO at the same time. However, before such a clock mismatch can occur, PHERR goes high and, if externally connected to PHINIT, will initialize the FIFO provided PHINIT remains high for at least two byte clocks. One to three 16-bit words of data will be lost during the initialization of the FIFO.
OSCILLATOR 155.52 MHz 20 ppm
TXREFCLK PCLK DIVIDER INTERNAL PCLK CLOCK DATA 16 PICLK TXD[0:15] TIMING GENERATOR FIFO PLL
PHERR PHINIT
CENTERS FIFO
CUSTOMER LOGIC
LOCKDET TA16 TRANSPONDER
1-1020(F)
Figure 4. Block Diagram Timing Mode 1
18 18
Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
high, the customer logic should start sending idle or dummy bytes to the TA16 on the TXD[0:15] bus. This should continue until PHERR goes low. The FIFO is initialized two-to-eight byte clocks after PHINIT goes high for two byte clocks. PHERR goes low after the FIFO is initialized. Upon detecting a low on PHERR, the customer logic can start sending real data bytes on TXD[0:15]. The two timing loops (PCLK to PICLK and PHERR to PHINIT) do not have to be of equal length.
Timing Characteristics (continued)
Input Timing Mode 2
To avoid the loss of data, idle or dummy bytes should be sent on the TXD[0:15] bus whenever PHERR goes high. In the configuration shown in Figure 5, the PHERR signal is used as an input to the customer logic. Upon detecting a high on the PHERR signal, the customer logic should return a high signal, one that remains high for at least two byte-clock cycles, to the PHINIT input of the TA16. Also, when PHERR goes
OSCILLATOR 155.52 MHz 20 ppm
TXREFCLK PCLK DIVIDER INTERNAL PCLK CLOCK DATA 16 PICLK TXD[0:15] TIMING GENERATOR PHERR D PHINIT Q CUSTOMER LOGIC LOCKDET TA16 TRANSPONDER
1-1021(F)
PLL
FIFO
CENTERS FIFO
Figure 5. Block Diagram Timing Mode 2
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Timing Characteristics (continued)
Forward Clocking
In some applications, it is necessary to forward-clock the data in a SONET/SDH system. In this application, the reference clock from which the high-speed serial clock is synthesized and the parallel data clock both originate from the same source on the customer application circuit. The timing control logic in theTA16 transponder transmitter automatically generates an internal load signal that has a fixed relationship to the reference
clock. The logic takes into account the variation of the reference clock to the internal load signal over temperature and voltage. The connections required to implement this clocking method are shown in Figure 6. The setup and hold times for PICLK to TxD[0:15] must be met by the customer logic. Possible problems: to meet the jitter generation specifications required by SONET/SDH, the jitter of the reference clock must be minimized. It could be difficult to meet the SONET jitter generation specifications using a reference clock generated from the customer logic.
OSCILLATOR 155.52 MHz 20 ppm
CLOCK BUFFER
TXREFCLK
TXREFCLK PCLK DIVIDER INTERNAL PCLK CLOCK DATA 16 PICLK TXD[0:15] TIMING GENERATOR FIFO PLL
PHERR PHINIT
CENTERS FIFO
CUSTOMER LOGIC
LOCKDET TA16 TRANSPONDER
Figure 6. Forward Clocking of the TA16 Transmitter
1-1122(F)
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
on the third PICLK after LOCKDET goes active. The PCLK-to-PICLK delay (tD) can have any value before the FIFO is initialized. The tD is fixed at the third PICLK after LOCKDET goes active. Once the FIFO is initialized, PCLK and PICLK cannot drift more than 5.2 ns; tCH cannot be more than 5.2 ns.
Timing Characteristics (continued)
PCLK-to-PICLK Timing
After powerup or RESET, the LOCKDET signal will go active, signifying that the PLL has locked to the clock provided on the TXREFCLK input. The FIFO is initialized
PCLK
tD
tD
PICLK
1ST
2ND
3RD tCH tCH
LOCKDET ACTIVE
PCLK-TO-PICLK DELAY IS FIXED AND FIFO IS INITALIZED AT THE THIRD RISING EDGE OF PICLK AFTER LOCKDET GOES ACTIVE.
1123(F)
Figure 7. PCLK-to-PICLK Timing
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Timing Characteristics (continued)
PHERR/PHINIT
Case 1-- PHERR and PHINIT are shorted on the printed-circuit board: PHINIT would go high whenever there is a potential timing mismatch between PCLK and PICLK. PHINIT would remain high as long as the timing mismatch between PCLK and PICLK. If PHINIT is high for more than two byte clocks, the FIFO will be initialized. PHINIT will initialize the FIFO two-to-eight byte clocks after it is high for at least two byte clocks, PHERR (and thus PHINIT) goes active once the FIFI is initialized.
Case 2--PHERR signal is input to the customer logic and the customer logic outputs a signal to PHINIT: Another possible configuration is where the PHERR signal is input into the customer logic and the customer logic sends an output to the PHINIT input. However, the customer logic must ensure that, upon detecting a high on PHERR, the PHINIT signal remains high for more than two byte clocks. If PHINIT is high for less than two byte clocks, the FIFO is not guaranteed to be initialized. Also, the customer logic must ensure that PHINIT goes low after the FIFO is initialized (PHERR goes low).
2 BYTE CLOCKS
2--8 BYTE CLOCKS
PHERR
MINIMUM PULSE WIDTH REQUIRED TO CENTER THE FIFO
PHINIT
CUSTOMER ASIC SENDS A MINIMUM PULSE WIDTH OF 2 BYTE CLOCKS UPON DETECTING A HIGH ON PHERR
PCLK
PICLK
INTERNAL PCLK
PHERR GOES HIGH ON DETECTING A FIFO TIMING ERROR
FIFO IS INITIALIZED 2--8 BYTE CLOCKS AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS
1125(F)
Figure 8. PHERR/PHINIT Timing
tSTXD PICLKP
tHTXD
TXD[0:15]
1027(F)
Figure 9. ac Input Timing 22 22 Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics (continued)
Table 9. Transmitter ac Timing Characteristics Symbol tSTXD tHTXD -- -- tD Description TxD[0:15] Setup Time w. r. t. PICLK TxD[0:15] Hold Time w. r. t. PICLK PCLKP/N Duty Cycle PICLKP/N Duty Cycle PCLK -to-PICLK Drift After FIFO is Centered Min 1.5 0.5 40 40 -- Max -- -- 60 60 5.2 Unit ns ns % % ns
Table 10. Receiver ac Timing Characteristics Symbol -- -- tPPOUT tSPOUT tHPOUT Description POCLK Duty Cycle RxD[15:0] Rise and Fall Time1 POCLK Low to RxD[15:0] Valid prop. delay RxD[15:0] and FP Setup Time w. r. t. POC LK RxD[15:0] and FP Hold Time w. r. t. POCLK Min 45 -- -1 2 2 Max 55 1.0 1 -- -- Unit % ns ns ns ns
1. 20% to 80%; 330 to GND
POCLKP
tPPOUT
FP RXD[15:0]
tSPOUT
tHPOUT
1-1022(F)
Figure 10. Receiver Output Timing Diagram
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Timing Characteristics (continued)
Receiver Framing
Figure 11 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. Both the frame and byte boundaries are recognized upon receipt of the first A2 byte following three consecutive A1 bytes. The third A2 byte is the first data byte to be reported with the correct byte alignment on the outgoing data bus (RxD[15:0]). Concurrently, the frame pulse (FP) is set high for one POCLK cycle.
RECOVERED CLOCK
The frame and byte boundary detection block is activated by the rising edge of OOF and stays active until the first FP pulse. Figure 12 shows the frame and byte boundary detection activation by a rising edge of OOF and deactivation by the first FP pulse. Figure 13 shows the frame and byte boundary detection by the activation of a rising edge of OOF and deactivation by the FRAMEN input.
OOF
SERIAL DATA A1 A1 A1 A2 A2 A2 A2 A2 A2
RXD[15:0]
A1, A1 INVALID DATA
A1, A1
A1, A1
A2, A2
A2, A2
A2, A2
A2, A2
VALID DATA
ROCLK
FP
1-1023(F)r.3
Figure 11. Frame and Byte Detection
BOUNDARY DETECTION ENABLED OOF
FP
SEARCH
1-1024(F)
Figure 12. OOF Timing (FRAMEN = High)
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Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics (continued)
BOUNDARY DETECTION ENABLED OOF
FRAMEN
FP
SEARCH
1-1025(F)
Figure 13. FRAMEN Timing
TA16 TRANSPONDER MULTIPLEXER SONET/SDH INTERFACE IC (VCC = 3.3 V) 330 330 TXREFCLKP TXREFCLKN 50 TRANSMISSION LINES CONNECTOR PLL CLOCK SYNTHESIZER 100 CONNECTOR 60
DIFFERENTIAL INTERFACE
TA16 TRANSPONDER MULTIPLEXER SONET/SDH INTERFACE IC (VCC = 3.3 V) 330 TXREFCLKP TXREFCLKN 0.1 F 50 TRANSMISSION LINES PLL CLOCK SYNTHESIZER 300
FOR A SINGLE-ENDED INPUT, THE INPUT IMPEDANCE IS EQUIVALENT TO 60 .
SINGLE-ENDED INTERFACE
Figure 14. Interfacing to the TxRefClk Input
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Qualification and Reliability
To help ensure high product reliability and customer satisfaction, Agere is committed to an intensive quality program that starts in the design phase and proceeds through the manufacturing process. Optoelectronics modules are qualified to Agere internal standards using MIL-STD-883 test methods and procedures and using sampling techniques consistent with Telcordia Technologies * requirements. This qualification program fully meets the intent of Telcordia Technologies reliability practices TR-NWT-000468 andTA-TSY-000983. In addition, the Agere Optoelectronics design, development, and manufacturing facility has been certified to be in full compliance with the latest ISO-9001 Quality System Standards.
* Telcordia Technologies is a trademark of Telcordia Technologies, Inc. ISO is a registered trademark of the International Organization for Standardization.
Laser Safety Information
Class I Laser Product
All versions of theTA16-type transponders are classified as Class I laser products per FDA/CDRH, 21 CFR 1040 Laser Safety requirements. The transponders have been registered/certified with the FDA under Accession Number 8720009. All versions are classified as Class I laser products per IEC 60825-1:1993. CAUTION: Use of controls, adjustments, and procedures other than those specified herein may result in hazardous laser radiation exposure. This product complies with 21 CFR 1040.10 and 1040.11. 8.8 m/125 m single-mode pigtail with 900 m tight buffer jacket and connector. Wavelength = 1.3 m, 1.5 m. Maximum power = 1.6 mW. Product is not shipped with power supply. Because of size constraints, laser safety labeling is not affixed to the module but is attached to the outside of the shipping carton.
NOTICE Unterminated optical connectors can emit laser radiation. Do not view with optical instruments.
Electromagnetic Emissions and Immunity
The TA16 transponder will be tested against CENELEC EN50 081 part 1 and part 2, FCC 15, Class B limits for emissions. The TA16 transponder will be tested against CENELEC EN50 082 part 1 immunity requirements.
IEC is a registered trademark of The International Electrotechnical Commission.
26
Agere Systems Inc.
Data Sheet March 2001
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Outline Diagram
Dimensions are in inches and (millimeters).
0.50 (12.7) 3.600 (91.44)
0.28 (7.11)
TRANSMITTER 0.65 (16.51) RECEIVER
2.600 (66.04)
0.22 (5.59) 0.500 (12.70)
0.75 (19.05)
1.50 (38.10)
0.450 (11.43) 0.30 (7.62) PIN 1 1.80 (45.72) 1.5 (38.1) MAX 34.5 (875) 43.0 (1100)
0.45 (11.43) CL 0.92 (22.37) 1.30 (33.02) 1.840 (46.74)
TX
RX
0.380 (9.65)
0.45 (11.43)
160-PIN JAE CONNECTOR MAT'G P/N WR-160PB-VF50-A3
MOUNTING HOLES (3 PLACES) M2.5 x 0.45 (METRIC) 2 mm MAXIMUM LENGTH INTO PACKAGE
1-1012(F).d
Agere Systems Inc.
27
TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Data Sheet March 2001
Ordering Information
ORDER CODE: BASIC PART NUMBER STM LEVEL 16 = STM-16 (SONET OC-48) APPLICATION N1 = I-16, 1310 nm, intraoffice/(SONET short reach) S1 = S-16.1, 1310 nm, short hauL (SONET IR-1) S2 = S-16.2, 1550 nm, short haul (SONET IR-2) L1 = L-16.1, 1310 nm, long hauL (SONET LR-1) L2 = L-16.2, 1550 nm, long haul (SONET LR-2) CONNECTOR* C = SC F = FC TA 16 - XX - X - XX OPTIONS
* Other connectors may be made available.
Table 11. Ordering Information Code TA16N1CAA TA16N1FAA TA16S1CAA TA16S1FAA TA16S2CAA TA16S2FAA TA16L1CAA TA16L1FAA TA16L2CAA TA16L2FAA Application 1310 nm, Intraoffice 1310 nm, Intraoffice 1310 nm, Short Haul 1310 nm, Short Haul 1550 nm, Short Haul 1550 nm, Short Haul 1310 nm, Long Haul 1310 nm, Long Haul 1550 nm, Long Haul 1550 nm, Long Haul Connector SC FC/PC SC FC/PC SC FC/PC SC FC/PC SC FC/PC Comcode 108440066 108440074 108432907 108432915 108432923 108432931 108432865 108432873 108432881 108432899
Related Product Information
Table 12. Related Product Information Description Using the Lucent Technologies Transponder Test Board Application Note Document Number AP00-017OPTO
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liabi lity is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A.
March 2001 DS01-119OPTO (Replaces DS00-259OPTO)

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